ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 322

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

26.10.4
26.10.5
8077H–AVR–12/09
EVCTRL – DAC Event Control Register
TIMCTRL – DAC Timing Control Register
• Bit 0 - LEFTADJ: DAC Left-Adjust Value
If this bit is set, CH0DATA and CH1DATA are left-adjusted.
• Bits 7:3 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 2:1 - EVSEL[2:0]: DAC Event Channel Input Selection
These bits define which channel from the Event System that is used for triggering a DAC
conversion.
Table 26-3
Table 26-3.
• Bit 7 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bits 6:4 - [2:0]: - CONINTVAL - DAC Conversion Interval
These bits control the minimum interval between two successive conversions. The interval must
be set relative to the Peripheral clock (clk
the result from the previous conversion has settled. The DAC Conversion Interval should never
be set lower than 1 µs during single channel operation, and not lower than 1.5 µs during dual
channel (S/H) operation.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x03
Read/Write
Initial Value
EVSEL[2:0]
000
001
010
011
100
101
110
111
shows the available selections.
R
7
0
R
-
7
0
-
DAC Event input Selection
R/W
6
1
R
6
0
-
Group Configuration
CONINTVAL[2:0]
R/W
R
5
1
5
0
-
0
1
2
3
4
5
6
7
PER
R/W
R
4
0
4
0
-
) to ensure that a new conversion is not started until
Description
Event channel 0 as input to DAC
Event channel 1 as input to DAC
Event channel 2 as input to DAC
Event channel 3 as input to DAC
Event channel 4 as input to DAC
Event channel 5 as input to DAC
Event channel 6 as input to DAC
Event channel 7 as input to DAC
R/W
R
3
0
3
0
-
R/W
R/W
2
0
2
0
REFRESH[3:0]
EVSEL[2:0]
R/W
R/W
1
0
1
0
XMEGA A
R/W
R/W
0
0
0
1
TIMCTRL
EVCTRL
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