ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 33

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

4.16.6
8077H–AVR–12/09
LOCKBITS - Non-Volatile Memory Lock Bit Register
• Bit 5:4 - BODACT[1:0]: BOD operation in active mode
The BODACT fuse bits set the BOD operation mode when the device is in active and idle mode
of operation. For details on the BOD and BOD operation modes refer to
Out Detection” on page
Table 4-6.
• Bit 3 - EESAVE: EEPROM memory is preserved through the Chip Erase
A chip erase command will normally erase the Flash, EEPROM and internal SRAM. If the
EESAVE fuse is programmed, the EEPROM is not erased during chip erase. In case EEPROM
is used to store data independent of software revision, the EEPROM can be preserved through
chip erase.
Table 4-7.
Changing of the EESAVE fuse bit takes effect immediately after the write time-out elapses.
Hence, it is possible to update EESAVE and perform a chip erase according to the new setting
of EESAVE without leaving and re-entering programming mode
• Bit 2:0 - BODLEVEL[2:0] - Brown out detection voltage level
The BODLEVEL fuse bits sets the nominal BOD level value. During power-on the device is kept
in reset until the V
that the BOD level is set lower than the V
normal operation, refer to
nominal values, see
• Bit 7:6 - BLBB[1:0]: Boot Lock Bit Boot Loader Section
These bits indicate the locking mode for the Boot Loader Section. Even though the BLBB bits
are writable, they can only be written to a stricter locking. Resetting the BLBB bits is only possi-
ble by executing a Chip Erase Command.
Bit
+0x07
Read/Write
Initial Value
BODACT[1:0]
EESAVE
00
01
10
11
0
1
BOD operation modes in Active and Idle mode
EEPROM memory through Chip Erase
R/W
7
1
Description
Reserved
BOD enabled in sampled mode
BOD enabled continuously
BOD Disabled
Description
EEPROM is preserved during chip erase
EEPROM is not preserved during chip erase
CC
BLBB[1:0]
Table 9-2 on page
level has reached the programmed BOD level. Due to this always ensure
106.
R/W
6
1
Section 9.4 ”Reset Sources” on page 104
R/W
5
1
BLBA[1:0]
106.
CC
R/W
level, also if the BOD is not enabled and used during
4
1
R/W
3
1
BLBAT[1:0]
R/W
2
1
R/W
for details. For BOD level
1
1
LB[1:0]
Section 9.4.2 ”Brown-
XMEGA A
R/W
0
1
LOCKBITS
33