ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 312

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

25.17.3
8077H–AVR–12/09
INTCTRL - ADC Channel Interrupt Control registers
Table 25-13. ADC MUXNEG Configuration, INPUTMODE[1:0] = 10, Differential without gain
Table 25-14. ADC MUXNEG Configuration, INPUTMODE[1:0] = 11, Differential with gain
• Bit 0 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 – INTMODE: ADC Interrupt Mode
These bits select the interrupt mode for channel n according to
Table 25-15. ADC Interrupt mode
Bit
+0x02
Read/Write
Initial Value
INTMODE[1:0]
MUXNEG[1:0]
MUXNEG[1:0]
00
01
10
11
00
01
10
11
00
01
10
11
R
7
0
-
Group Configuration
R
6
0
-
Group Configuration
Group Configuration
COMPLETE
BELOW
ABOVE
PIN0
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
R
5
0
-
R
4
0
-
Interrupt mode
Conversion Complete
Compare Result Below Threshold
Reserved
Compare Result Above Threshold
R/W
3
0
INTMODE[1:0}
R/W
2
0
Table
Analog input
Analog input
ADC0 pin
ADC1 pin
ADC2 pin
ADC3 pin
ADC4 pin
ADC5 pin
ADC6 pin
ADC7 pin
25-15.
R/W
1
0
INTLVL[1:0]
XMEGA A
R/W
0
0
INTCTRL
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