ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 23

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

4.7
4.7.1
4.8
4.8.1
4.9
4.10
8077H–AVR–12/09
EEPROM
I/O Memory
External Memory
Data Memory and Bus Arbitration
Data Memory Mapped EEPROM Access
General Purpose I/O Registers
XMEGA has EEPROM memory for non-volatile data storage. It is addressable either in as a sep-
arate data space (default), or it can be memory mapped and accessed in normal data space.
The EEPROM memory supports both byte and page access.
The EEPROM address space can optionally be mapped into the Data Memory space to allow
highly efficient EEPROM reading and EEPROM buffer loading. When doing this EEPROM is
accessible using load and store instructions. Memory mapped EEPROM will always start at
hexadecimal address location 0x1000.
The status and configuration registers for all peripherals and modules, including the CPU, are
addressable through I/O memory locations in the data memory space. All I/O locations can be
accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, transferring data
between the 32 general purpose registers in the Register File and the I/O memory. The IN and
OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly. In the
address range 0x00 - 0x1F, specific bit manipulating and checking instructions are available.
The I/O memory definition for an XMEGA device is shown in "Register Summary" in the device
data sheet.
The lowest 16 I/O Memory addresses is reserved for General Purpose I/O Registers. These reg-
isters can be used for storing information, and they are particularly useful for storing global
variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC
instructions.
XMEGA has up to 4 ports dedicated to External Memory, supporting external SRAM, SDRAM,
and memory mapped peripherals such as LCD displays or other memory mapped devices. For
details refer to the External Bus interface (EBI) description. The External Memory address space
will always start at the end of Internal SRAM.
As the Data Memory organized as four separate sets of memories, the different bus masters
(CPU, DMA Controller read and DMA Controller write) can access different memories at the
same time. As
the DMA (DMA) Controller is transferring data from Internal SRAM to I/O Memory.
Figure 4-3 on page 24
shows, the CPU can access the External Memory while
XMEGA A
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