ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 52

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

5.9
5.10
5.11
5.12
8077H–AVR–12/09
Error detection
Software Reset
Protection
Interrupts
The DMA controller can detect erroneous operation. Error conditions are detected individually
for each DMA channel, and the error conditions are:
Both the DMA controller and a DMA channel can be reset from the user software. When the
DMA controller is reset, all registers associated with the DMA controller is cleared. A software
reset can only be done when the DMA controller is disabled. When a DMA channel is reset, all
registers associated with the DMA channel are cleared. A software reset can only be done when
the DMA channel is disabled.
In order to insure safe operation some of the channel registers are protected during a transac-
tion. When the DMA channel Busy flag (CHnBUSY) is set for a channel, the user can only
modify these registers and bits:
The DMA Controller can generate interrupts when an error is detected on a DMA channel or
when a transaction is complete for a DMA channel. Each DMA channel has a separate interrupt
vector, and there are different interrupt flags for error and transaction complete.
If repeat is not enabled the transaction complete flag is set at the end of the Block Transfer. If
unlimited repeat is enabled, the transaction complete flag is also set at the end of each Block
Transfer.
• Write to memory mapped EEPROM memory locations.
• Reading EEPROM memory when the EEPROM is off (sleep entered).
• DMA controller or a busy channel is disabled in software during a transfer.
• CTRL register
• INTFLAGS register
• TEMP registers
• CHEN, CHRST, TRFREQ, REPEAT bits of the Channel CTRL register
• TRIGSRC register
XMEGA A
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