ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 327

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

26.10.12 OFFSETCAL – DAC Offset Calibration Register
26.11 Register Summary
8077H–AVR–12/09
Address
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
+0x06
+0x07
+0x08
+0x09
+0x10
+0x11
+0x12
+0x13
+0x14
+0x15
+0x16
+0x17
+0x18
+0x19
+0x1A
+0x1B
Name
CTRLB
OFFSETCAL
CH0DATAH
CH1DATAH
CH0DATAL
CH1DATAL
TIMCTRL
GAINCAL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EVCTRL
STATUS
CTRLC
CTRLA
• Bits 6:0 - GAINCAL[6:0]: DAC Gain Calibration value
These bits are used to compensate the gain error in the DAC. See
details on how to calibrate gain.
• Bit 7 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bits 6:0 - OFFSETCAL[6:0]: DAC Offset Calibration value
These bits are used to compensate the offset error in the DAC. See
for details on how to calibrate offset.
This is the I/O summary when the DAC is configured to give standard 12-bit results. I/O sum-
mary for 12-bit left adjusted will be similar, but with some changes in the data registers
CHnDATAL and CHnDATAH.
Bit
+0x09
Read/Write
Initial Value
Bit 7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit 6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CHSEL[1:0]
R
7
0
-
CONINTVAL[2:0]
Bit 5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
6
0
Bit 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
5
0
REFSEL[1:0]
CHDATA[7:0]
CHDATA[7:0]
CH1EN
Bit 3
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
OFFSETCAL[6:0]
4
0
GAINCAL[6:0]
OFFSETCAL[6:0]
R/W
CH0EN
3
0
Bit 2
-
-
-
-
-
-
-
-
-
-
-
-
-
REFRESH[3:0]
CHDATA[11:8]
CHDATA[11:8]
R/W
2
0
CH1TRIG
LPMODE
EVSEL[2:0]
CH1DRE
Bit 1
-
-
-
-
-
-
-
-
-
-
-
”Calibration” on page 319
R/W
”Calibration” on page 319
1
0
CH0TRIG
LEFTADJ
ENABLE
CH0DRE
XMEGA A
Bit 0
R/W
-
-
-
-
-
-
-
-
-
-
0
0
OFFSETCAL
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