ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 167

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

14.12.4
8077H–AVR–12/09
CTRLD - Control Register D
• Bit 7:5 – EVACT[2:0]: Event Action
These bits define the Event Action the timer will perform on an event according to
page
The EVSEL setting will decide which event source or sources that have the control in this case.
Table 14-5.
Selecting the any of the capture event action changes the behavior of the CCx registers and
related status and control bits to be used as for capture. The error status flag (ERRIF) will in this
configuration indicate a buffer overflow.
• Bit 4 – EVDLY: Timer Delay Event
When this bit is set, the selected event source is delayed by one peripheral clock cycle. This fea-
ture is intended for 32-bit input capture operation. Adding the event delay is necessary for
compensating for the carry propagation delay that is inserted when cascading two counters via
the Event System.
• Bit 3:0 – EVSEL[3:0]:Timer Event Source Select
These bits select the event channel source for the Timer/Counter. For the selected event chan-
nel to have any effect the Event Action bits (EVACT) must be set according to
the Event Action is set to capture operation, the selected event channel n will be the event chan-
nel source for CC channel A, and event channel (n+1)%8, (n+2)%8 and (n+3)%8 will be the
event channel source for CC channel B, C and D.
Bit
+0x03
Read/Write
Initial Value
167.
EVACT[2:0]
000
001
010
011
100
101
110
111
Timer Event Action Selection
R/W
7
0
EVACT[2:0]
R/W
6
0
Group Configuration
UPDOWN
RESTART
R/W
QDEC
CAPT
5
0
FRQ
OFF
PW
EVDLY
R/W
4
0
Event Action
None
Input Capture
Externally Controlled Up/ Down Count
Quadrature decode
Restart waveform period
Frequency Capture
Pulse Width Capture
Reserved
R/W
3
0
R/W
2
0
EVSEL[3:0]
R/W
1
0
XMEGA A
Table
R/W
0
0
Table 14-5 on
14-6. When
CTRLD
167