ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 166

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

14.12.3
8077H–AVR–12/09
CTRLC - Control Register C
• Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 2:0 – WGMODE[2:0]: Waveform Generation Mode
These bits select the Waveform Generation Mode, and control the counting sequence of the
Counter, the TOP value, the UPDATE condition, the Interrupt/event condition, and type of wave-
form that is generated, according to
No waveform generation is performed in normal mode of operation. For all other modes the
result from the waveform generator will only be directed to the port pins if the corresponding
CCxEN bit has been set to enable this. The port pin direction must be set as output.
Table 14-4.
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:0 – CMPx: Compare Output Value n
These bits allow direct access to the Waveform Generator's output compare value when the
Timer/Counter is set in “OFF” state. This is used to set or clear the WG output value when the
Timer/Counter is not running.
Bit
+0x02
Read/Write
Initial Value
WGMODE[2:0]
000
001
010
011
100
101
110
111
Timer Waveform Generation Mode
R
7
0
-
Configuration
NORMAL
DS_TB
Group
DS_B
R
DS_T
6
0
-
FRQ
SS
R
5
0
-
Table 14-4 on page
Mode of
operation
Normal
FRQ
Reserved
Single Slope
PWM
Reserved
Dual Slope PWM
Dual Slope PWM
Dual Slope PWM
R
4
0
-
CMPD
R/W
3
0
166.
Top
PER
CCA
-
PER
-
PER
PER
PER
CMPC
R/W
2
0
Update
TOP
TOP
-
BOTTOM
-
BOTTOM
BOTTOM
BOTTOM
CMPB
R/W
1
0
OVFIF/Event
TOP
TOP
-
BOTTOM
-
TOP
TOP and BOTTOM
BOTTOM
XMEGA A
CMPA
R/W
0
0
CTRLC
166