ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 154

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

14.6
8077H–AVR–12/09
Counter Operation
Figure 14-4. Period and Compare Double Buffering
When the CC channels is used for capture operation a similar Double buffering mechanism is
used, but the Buffer Valid flag is set on the capture event as shown in
the buffer and the corresponding CCx register acts like a FIFO. When the CC register is empty
or read, any contents in the buffer is passed to the CC register. The Buffer valid flag is passed to
the CCx Interrupt Flag (IF) which is them set and the optional interrupt is generated.
Figure 14-5. Capture Double Buffering
Both the CCx and CCxBUF registers are available in the I/O register address map. This allows
initialization and bypassing of the buffer register, and the double buffering feature.
Dependent of the mode of operation, the Counter is cleared, reloaded, incremented, or decre-
mented at each Timer/Counter clock input.
UPDATE
"capture"
"INT/DMA
request"
BV
IF
EN
EN
BV
CCxBUF
CCx
CNT
EN
EN
CNT
CCxBUF
=
CCx
"write enable"
"match"
"data"
Figure
XMEGA A
14-5. For capture
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