ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 247

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

21.10 USART in Master SPI Mode
21.11 USART SPI vs. SPI
8077H–AVR–12/09
samples per 10-bit frame compared to the previous from 160 to 320. Higher negative scale fac-
tor gives even finer granularity. There is a limit to how high the scale factor can be. A rule of
thumb is that the value 2
frame takes. For instance for 10-bit frames the minimum number of clock cycles is 160. This
means that the highest applicable scale factor is -6 (2
tings the scale factor can be increased.
Using the USART in Master SPI mode (MSPIM) requires the Transmitter to be enabled. The
Receiver can optionally be enabled to serve as the serial input. The XCK pin will be used as the
transfer clock.
As for USART a data transfer is initiated by writing to the DATA location. This is the case for both
sending and receiving data since the transmitter controls the transfer clock. The data written to
DATA is moved from the transmit buffer to the shift register when the shift register is ready to
send a new frame.
The Transmitter and Receiver interrupt flags and corresponding USART interrupts in Master SPI
mode are identical in function to the normal USART operation. The receiver error status flags
are not in use and is always read as zero.
Disabling of the USART transmitter or receiver in Master SPI mode is identical in function to the
normal USART operation.
The USART in Master SPI mode is fully compatible with the SPI regarding:
Since the USART in Master SPI mode reuses the USART resources, the use of the USART in
MSPIM is somewhat different compared to the XMEGA SPI module. In addition to differences of
the control register bits and no SPI slave support, the following features differ between the two
modules:
• Master mode timing diagram.
• The UCPHA bit functionality is identical to the SPI CPHA bit.
• The UDORD bit functionality is identical to the SPI DORD bit.
• The Transmitter USART in Master SPI mode includes buffering. The XMEGA SPI has no
• The Receiver in USART in Master SPI includes an additional buffer level.
• The SPI WCOL (Write Collision) bit is not included in USART in Master SPI mode.
• The SPI double speed mode (SPI2X) bit is not included. However, the same effect is
• Interrupt timing is not compatible.
• Pin control differs due to the master only operation of the USART in Master SPI mode.
transmit buffer.
achieved by setting BSEL accordingly.
BSCALE
must be at least half of the minimum number of clock cycles a
-6
= 64 < 160/2 = 80). For higher BSEL set-
XMEGA A
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