ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 50

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

5.3
5.3.1
5.3.2
5.4
8077H–AVR–12/09
DMA Transaction
Transfer Triggers
Block Transfer and Repeat
Burst Transfer
A complete DMA read and write operation between memories and/or peripherals is called a
DMA transaction. A transaction is done in data blocks and the size of the transaction (number of
bytes to transfer) is selectable from software and controlled by the block size and repeat counter
settings. Each block transfer is divided into smaller bursts.
The size of the block transfer is set by the Block Transfer Count Register, and can be anything
from 1 byte to 64 KBytes.
A repeat counter can be enabled to set a number of repeated block transfers before a transac-
tion is complete. The repeat is from 1 to 255 and unlimited repeat count can be achieved by
setting the repeat count to zero.
As the AVR CPU and DMA controller use the same data buses a block transfer is divided into
smaller burst transfers. The burst transfer is selectable to 1, 2, 4, or 8 bytes. This means that, if
the DMA acquires a data bus and a transfer request is pending it will occupy the bus until all
bytes in the burst transfer is transferred.
A bus arbiter controls when the DMA controller and the AVR CPU can use the bus. The CPU
always has priority, so as long as the CPU request access to the bus, any pending burst transfer
must wait. The CPU requests bus access when it executes an instruction that write or read data
to SRAM, I/O memory, EEPROM and the External Bus Interface. For more details on memory
access bus arbitration, refer to
Figure 5-1.
DMA transfers can only be started when a DMA transfer request is detected. A transfer request
can be triggered from software, from an external trigger source (peripheral) or from an event.
There are dedicated source trigger selections for each DMA channel. The available trigger
sources may vary from device to device, depending on the modules or peripherals that exist in
the device. Using a transfer trigger for a module or peripherals that does not exist will have no
effect, for a list of all transfer triggers refer to
page
58.
Four-byte burst mode
DMA transaction.
Burst transfer
Block size: 12 bytes
”Data Memory” on page
DMA transaction
”TRIGSRC - DMA Channel Trigger Source” on
Repeat count: 2
22.
Block transfer
XMEGA A
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