ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 157

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

14.7.1
8077H–AVR–12/09
Input Capture
Event Source Selection for capture operation
The Event Action setting in the Timer/Counter will determine the type of capture that is done.
The CC channel to use must be enabled individually before capture can be done. When the cap-
ture condition occur, the Timer/Counter will time-stamp the event by copying the current value in
the Count register into the enabled CC channel register.
When an I/O pin is used as event source for the Capture, the pin must be configured for edge
sensing. For details on sense configuration on I/O pins, refer to
page
will be stored in the Most Significant Bit (MSB) of the Capture register after a Capture. If the
MSB of the Capture register is zero, a falling edge generated the Capture. If the MSB is one, a
rising edge generated the Capture.
Three different types of capture are available.
Selecting the input capture event action, makes the enabled capture channel perform an input
capture on any event. The interrupt flags will be set and indicate that there is a valid capture
result in the corresponding CC register. Equally the buffer valid flags indicates valid data in the
buffer registers. Refer to
buffering.
The counter will continuously count for BOTTOM to TOP, then restart on BOTTOM as shown in
Figure
Figure 14-9. Input capture timing
CNT
134. If the Period register value is set lower than 0x8000, the polarity of the I/O pin edge
14-9. The figure also shows four capture events for one capture channel.
events
Event System
TOP
BOT
CH0MUX
CH1MUX
CH7MUX
Capture 0
”Double Buffering” on page 153
Event channel 0
Event channel 1
Event channel 7
Capture 1
Capture 2
Rotate
for more details on capture double
Event Source Selection
”Input Sense Configuration” on
CCA capture
CCB capture
CCC capture
CCD capture
Capture 3
XMEGA A
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