ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 169

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

14.12.7
14.12.8
8077H–AVR–12/09
INTCTRLB - Interrupt Enable Register B
CTRLFCLR/CTRLFSET - Control Register F Clear/Set
• Bit 3:2 - ERRINTLVL[1:0]:Timer Error Interrupt Level
These bits enable the Timer Error Interrupt and select the interrupt level as described in
rupts and Programmable Multi-level Interrupt Controller” on page
• Bit 1:0 - OVFINTLVL[1:0]:Timer Overflow/Underflow Interrupt Level
These bits enable the Timer Overflow/Underflow Interrupt and select the interrupt level as
described in
• Bit 7:0 - CCxINTLVL[1:0] - Compare or Capture x Interrupt Level:
These bits enable the Timer Compare or Capture Interrupt and select the interrupt level as
described in
This register is mapped into two I/O memory locations, one for clearing (CTRLxCLR) and one for
setting the register bits (CTRLxSET) when written. Both memory locations yield the same result
when read.
The individual status bit can be set by writing a one to its bit location in CTRLxSET, and cleared
by writing a one to its bit location in CTRLxCLR. This each bit to be set or cleared without using
of a Read-Modify-Write operation on a single register.
• Bit 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x07
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
Bit
+0x09
Read/Write
Initial Value
”Interrupts and Programmable Multi-level Interrupt Controller” on page
”Interrupts and Programmable Multi-level Interrupt Controller” on page
R/W
CCDINTLVL[1:0]
7
0
R
R
7
0
7
0
-
-
R/W
R
R
6
0
6
0
6
0
-
-
R/W
R
R
5
0
5
0
-
-
5
CCCINTLVL[1:0]
0
R
4
0
4
R
0
-
-
R/W
4
0
R/W
R
3
0
3
0
R/W
CMD[1:0]
CMD[1:0]
CCBINTLVL[1:0]
3
0
R/W
R
2
0
2
0
R/W
2
0
123.
LUPD
LUPD
R/W
R/W
1
0
1
0
R/W
CCAINTLVL[1:0]
1
0
R/W
R/W
DIR
DIR
XMEGA A
0
0
0
0
R/W
0
0
123.
123.
CTRLFCLR
CTRLFSET
INTCTRLB
”Inter-
169