ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 198

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

18.2.1
18.2.2
18.2.3
18.2.4
18.3
18.3.1
8077H–AVR–12/09
Register Description
Clock selection
Clock domains
Power domains
Interrupts and events
CTRL - Control Register
An external 32.768 kHz crystal oscillator must be used as clock source. Two different frequency
outputs are available form this, and the RTC clock input can be 1.024 kHz or 1 Hz.
The RTC is asynchronous, meaning it operates from a different clock source and independently
of the main System Clock and its derivative clocks such as the Peripheral Clock. For Control and
Count register updates it will take a number of RTC clock and/or Peripheral clock cycles before
an updated register value is available or until a configuration change has effect on the RTC. This
synchronization time is described for each register.
The Peripheral clock must be eight times faster than the RTC clock (1.024 kHz or 1 Hz) when
any the Control and Count register is accessed (read or written), expect 12 times faster when
the Count register is written.
For devices where the RTC is located in the V
correctly with no V
source is available. A dynamic power-switch is used to automatically switch from V
the V
age is restored, the power is automatically switched back to V
The RTC can generate both interrupts and events. The RTC will give a compare interrupt
request and/or event when the counter value equals the Compare register value. The RTC will
give an overflow interrupt request and/or event when the counter value equals the Period regis-
ter value. The overflow will also reset the counter value to zero.
Due to the asynchronous clock domains event will only will only be generated for every third
overflow or compare if the period register is zero. If the period register is one, events will only be
generated for every second overflow or compare. When the period register is equal to or above
two, events will trigger at every overflow or compare just as the interrupt request.
• Bits 7:1 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x00
Read/Write
Reset Value
BAT
domain if V
7
R
0
CC
CC
available. When running from the V
falls below the operating voltage level for the device. When the V
6
R
0
5
R
0
4
R
0
BAT
power domain this enables the RTC to function
3
R
0
BAT
power domain, only the 1 Hz clock
2
-
R
0
CC
.
1
-
R
0
ENABLE
XMEGA A
R/W
0
0
CC
domain to
CTRL
CC
volt-
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