ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 369

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

30.11.2
8077H–AVR–12/09
NVM Flash Commands
Figure 30-2. Flash addressing for self-programming
The NVM commands that can be used for accessing the Flash Program Memory, Signature
Row and Calibration Row are listed in
For self-programming of the Flash, the Trigger for Action Triggered Commands is to set the
CMDEX bit in the NVM CTRLA register (CMDEX). The Read Triggered Commands are trig-
gered by executing the (E)LPM instruction (LPM). The Write Triggered Commands is triggered
by a executing the SPM instruction (SPM).
The Change Protected column indicate if the trigger is protected by the Configuration Change
Protection (CCP). This is a special sequence to write/execute the trigger during self-program-
ming, for more details refer to
CCP is not required for external programming. The two last columns shows the address pointer
used for addressing, and the source/destination data register.
Section 30.11.1.1 on page 367
algorithm for each NVM operation.
FLASHEND
FPAGE
00
01
02
PROGRAM MEMORY
Z-Pointer
BIT
PAGE
WITHIN THE FLASH
PAGEMSB
PAGE ADDRESS
”CCP - Configuration Change Protection Register” on page
through
FPAGE
Table
Section 30.11.2.14 on page 374
30-2.
WORDMSB
FWORD
WORD ADDRESS
WITHIN A PAGE
INSTRUCTION WORD
1
0/1
0
PAGE
Low/High Byte select for (E)LPM
explain in details the
XMEGA A
00
01
02
PAGEEND
FWORD
369
13.