AT91SAM9XE512-CU Atmel, AT91SAM9XE512-CU Datasheet - Page 122

• Manufacturer Part Number: AT91SAM9XE512-CU
• Description: MCU ARM9 512K FLASH 217-BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE512-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 96
• Interface Type: EBI/Ethernet/SPI/TWI/USART/USB
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 6
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 180 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.3
Functional Description
The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems.
The PIT provides a programmable overflow counter and a reset-on-read feature. It is built
around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at
Master Clock /16.
The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the
field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to
0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Regis-
ter (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in
PIT_MR).
Writing a new PIV value in PIT_MR does not reset/restart the counters.
When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register
(PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging
the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last
read of PIT_PIVR.
When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register
(PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For exam-
ple, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer
interrupt clears the interrupt by reading PIT_PIVR.
The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on
reset). The PITEN bit only becomes effective when the CPIV value is 0.
Figure 17-2
illustrates
the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until
the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again.
The PIT is stopped when the core enters debug state.
AT91SAM9XE128/256/512 Preliminary
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6254C–ATARM–22-Jan-10