AT91SAM9XE512-CU Atmel, AT91SAM9XE512-CU Datasheet - Page 812

• Manufacturer Part Number: AT91SAM9XE512-CU
• Description: MCU ARM9 512K FLASH 217-BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE512-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 96
• Interface Type: EBI/Ethernet/SPI/TWI/USART/USB
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 6
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 180 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

43.8
43.9
Table 43-24. Power-On-Reset Characteristics
43.10 Power-down Sequence
812
Symbol
V
V
T
RES
th+
th-
Core Power Supply POR Characteristics
Power-up Sequence
AT91SAM9XE128/256/512 Preliminary
Parameter
Threshold Voltage Rising
Threshold Voltage Falling
Reset Time
The board design must comply with the power-up guidelines below to guarantee reliable opera-
tion of the device. Any deviation from these sequences may prevent the device from booting.
VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that
these power sources reach their target values prior to the release of POR.
To ensure a working system, VDDIOP0, VDDIOP1, and VDDIOM should be established to
power external memories and I/Os before the first acces. This can be achieved if VDDIOP0,
VDDIOP1, and VDDIOM are powered before VDDCORE.
To ensure external memories and I/Os are powered until the last access, switch off VDDIOM,
VDDIOP0 and VDDIOP1 power supplies after or at the same time as switching off VDDCORE.
No power-up or power-down restrictions apply to VDDBU, VDDPLL and VDDANA.
Conditions
Minimum Slope of +2.0V/200ms
1.35
1.25
Min
100
1.50
1.30
Typ
200
6254C–ATARM–22-Jan-10
1.59
Max
1.40
350
Units
µs
V
V