AT91SAM9XE512-CU Atmel, AT91SAM9XE512-CU Datasheet - Page 854

• Manufacturer Part Number: AT91SAM9XE512-CU
• Description: MCU ARM9 512K FLASH 217-BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE512-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 96
• Interface Type: EBI/Ethernet/SPI/TWI/USART/USB
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 6
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 180 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

iv
AT91SAM9XE128/256/512 Preliminary
21 AT91SAM9XE Bus Matrix .................................................................... 159
22 AT91SAM9XE128/256/512 External Bus Interface ............................ 169
23 Static Memory Controller (SMC) ......................................................... 195
24 SDRAM Controller (SDRAMC) ............................................................ 239
21.1 Description .......................................................................................................159
21.2 Memory Mapping .............................................................................................159
21.3 Special Bus Granting Techniques ....................................................................159
21.4 Arbitration .........................................................................................................160
21.5 Bus Matrix (MATRIX) User Interface ................................................................163
21.6 Chip Configuration User Interface ....................................................................167
22.1 Description .......................................................................................................169
22.2 Block Diagram ..................................................................................................170
22.3 I/O Lines Description ........................................................................................171
22.4 Application Example .........................................................................................173
22.5 Product Dependencies .....................................................................................176
22.6 Functional Description ......................................................................................176
22.7 Implementation Examples ................................................................................185
23.1 Description .......................................................................................................195
23.2 I/O Lines Description ........................................................................................195
23.3 Multiplexed Signals ..........................................................................................195
23.4 Application Example .........................................................................................196
23.5 Product Dependencies .....................................................................................196
23.6 External Memory Mapping ...............................................................................197
23.7 Connection to External Devices .......................................................................197
23.8 Standard Read and Write Protocols .................................................................202
23.9 Automatic Wait States ......................................................................................211
23.10 Data Float Wait States .....................................................................................215
23.11 External Wait ....................................................................................................220
23.12 Slow Clock Mode .............................................................................................226
23.13 Asynchronous Page Mode ...............................................................................229
23.14 Static Memory Controller (SMC) User Interface ...............................................232
24.1 Description .......................................................................................................239
24.2 I/O Lines Description ........................................................................................239
24.3 Application Example .........................................................................................240
24.4 Product Dependencies .....................................................................................242
6254C–ATARM–22-Jan-10