AT91SAM9XE512-CU Atmel, AT91SAM9XE512-CU Datasheet - Page 712

• Manufacturer Part Number: AT91SAM9XE512-CU
• Description: MCU ARM9 512K FLASH 217-BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE512-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 96
• Interface Type: EBI/Ethernet/SPI/TWI/USART/USB
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 6
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 180 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

39.5.1.2
39.5.1.3
712
AT91SAM9XE128/256/512 Preliminary
USB Bus Transactions
USB Transfer Event Definitions
Each transfer results in one or more transactions over the USB bus. There are three kinds of
transactions flowing across the bus in packets:
As indicated below, transfers are sequential events carried out on the USB bus.
Table 39-3.
Notes:
A status transaction is a special type of host-to-device transaction used only in a control transfer.
The control transfer must be performed using endpoints with no ping-pong attributes. According
to the control sequence (read or write), the USB device sends or receives a status transaction.
Control Transfers
Interrupt IN Transfer
(device toward host)
Interrupt OUT Transfer
(host toward device)
Isochronous IN Transfer
(device toward host)
Isochronous OUT Transfer
(host toward device)
Bulk IN Transfer
(device toward host)
Bulk OUT Transfer
(host toward device)
1. Setup Transaction
2. Data IN Transaction
3. Data OUT Transaction
1. Control transfer must use endpoints with no ping-pong attributes.
2. Isochronous transfers must use endpoints with ping-pong attributes.
3. Control transfers can be aborted using a stall handshake.
USB Transfer Events
(1) (3)
(2)
(2)
• Setup transaction > Data IN transactions > Status
• Setup transaction > Data OUT transactions > Status
• Setup transaction > Status IN transaction
• Data IN transaction > Data IN transaction
• Data OUT transaction > Data OUT transaction
• Data IN transaction > Data IN transaction
• Data OUT transaction > Data OUT transaction
• Data IN transaction > Data IN transaction
• Data OUT transaction > Data OUT transaction
OUT transaction
IN transaction
6254C–ATARM–22-Jan-10