AT91SAM9XE512-CU Atmel, AT91SAM9XE512-CU Datasheet - Page 89

• Manufacturer Part Number: AT91SAM9XE512-CU
• Description: MCU ARM9 512K FLASH 217-BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE512-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 96
• Interface Type: EBI/Ethernet/SPI/TWI/USART/USB
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 6
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 180 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 14-5.
14.2.5
14.2.5.1
6254C–ATARM–22-Jan-10
Step
1
2
3
4
5
6
7
8
9
10
11
12
13
Device Operations
Programmer Action
Sets MODE and DATA signals
Clears NCMD signal
Waits for RDY low
Sets DATA signal in tristate
Clears NOE signal
Waits for NVALID low
Reads value on DATA Bus
Sets NOE signal
Waits for NVALID high
Sets DATA in output mode
Sets NCMD signal
Waits for RDY high
Flash Read Command
Read Handshake
Several commands on the Flash memory are available. These commands are summarized in
Table 14-3 on page
face running several read/write handshaking sequences.
When a new command is executed, the previous one is automatically achieved. Thus, chaining
a read command after a write automatically flushes the load buffer in the Flash.
This command is used to read the contents of the Flash memory. The read command can start
at any valid address in the memory plane and is optimized for consecutive reads. Read hand-
shaking can be chained; an internal address buffer is automatically increased.
Table 14-6.
Step
1
2
3
4
5
...
n
n+1
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
Read handshaking
Read handshaking
...
Write handshaking
Write handshaking
Read Command
87. Each command is driven by the programmer through the parallel inter-
AT91SAM9XE128/256/512 Preliminary
Device Action
Waits for NCMD low
Latch MODE and DATA
Clears RDY signal
Waits for NOE Low
Sets DATA bus in output mode and outputs
the flash contents.
Clears NVALID signal
Waits for NOE high
Sets DATA bus in input mode
Sets NVALID signal
Waits for NCMD high
Sets RDY signal
MODE[3:0]
DATA
DATA
ADDR1
CMDE
ADDR0
ADDR1
...
ADDR0
DATA[15:0]
READ
Memory Address LSB
Memory Address
*Memory Address++
*Memory Address++
...
Memory Address LSB
Memory Address
Input
DATA I/O
Input
Input
Input
Input
Tristate
Output
Output
Output
Output
X
Input
Input
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