AT91SAM9XE512-CU Atmel, AT91SAM9XE512-CU Datasheet - Page 838

• Manufacturer Part Number: AT91SAM9XE512-CU
• Description: MCU ARM9 512K FLASH 217-BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE512-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 96
• Interface Type: EBI/Ethernet/SPI/TWI/USART/USB
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 6
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 180 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

46.2
46.2.1
46.2.1.1
46.2.2
46.2.2.1
46.2.3
46.2.3.1
46.2.3.2
46.2.3.3
46.2.3.4
838
AT91SAM9XE128/256/512 Errata - Revision A parts
AT91SAM9XE128/256/512 Preliminary
Analog-to-Digital Converter (ADC)
Error Corrected Code Controller (ECC)
MultiMedia Card Interface (MCI)
ADC: Sleep Mode
ECC: Computation with a 1 clock cycle long NRD/NWE pulse
MCI: Busy signal of R1b responses is not taken in account
MCI: SDIO Interrupt does not work with slots other than A
MCI: Data Write Operation and number of bytes
MCI: Flag Reset is not correct in half duplex mode
Refer to
If Sleep mode is activated while there is no activity (no conversion is being performed), it will
take effect only after a conversion occurs.
To activate sleep mode as soon as possible, it is recommended to write successively, ADC
Mode Register (SLEEP) then ADC Control Register (START bit field), in order to start an analog-
to-digital conversion and then put ADC into sleep mode at the end of this conversion.
If the SMC is programmed with NRD/NWE pulse length equal to 1 clock cycle, HECC can't com-
pute the parity.
It is recommended to program SMC with a value higher than 1.
The busy status of the card during the response (R1b) is ignored for the commands CMD7,
CMD28, CMD29, CMD38, CMD42, CMD56. Additionally, for commands CMD42 and CMD56 a
conflict can occur on data line0 if the MCI sends data to the card while the card is still busy. The
behavior is correct for CMD12 command (STOP_TRANSFER).
None
If there is 1-bit data bus width on slots other than slot A, the SDIO interrupt can not be captured.
The sample is made on the wrong data line.
Problem Fix/Workaround
None
The Data Write operation with a number of bytes less than 12 is impossible.
The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The
BLKLEN or BCNT field are used to specify the real count number.
In half duplex mode, the reset of the flags ENDRX, RXBUFF, ENDTX and TXBUFE can be
incorrect. These flags are reset correctly after a PDC channel enable.
Problem Fix/Workaround
Problem/Fix Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Section 46.1 “Marking” on page
837.
6254C–ATARM–22-Jan-10