P89LPC9341FDH,512 NXP Semiconductors, P89LPC9341FDH,512 Datasheet - Page 57

• Manufacturer Part Number: P89LPC9341FDH,512
• Description: IC 80C51 MCU FLASH 8K 28-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC9341FDH,512

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 28-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8 bit, 4 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935288632512

NXP Semiconductors
P89LPC9331_9341_9351_9361
Product data sheet
7.30.8 ISP
7.30.9 Power-on reset code execution
without additional components. Two methods are available to accomplish IAP. A set of
predefined IAP functions are provided in a Boot ROM and can be called through a
common interface, PGM_MTP. Several IAP calls are available for use by an application
program to permit selective erasing and programming of flash sectors, pages, security
bits, configuration bytes, and device ID. These functions are selected by setting up the
microcontroller’s registers before making a call to PGM_MTP at FF03H. The Boot ROM
occupies the program memory space at the top of the address space from FF00H to
FEFFH, thereby not conflicting with the user program memory space.
In addition, IAP operations can be accomplished through the use of four SFRs consisting
of a control/status register, a data register, and two address registers. Additional details
may be found in the P89LPC9331/9341/9351/9361 User manual.
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal firmware to
facilitate remote programming of the P89LPC9331/9341/9351/9361 through the serial
port. This firmware is provided by NXP and embedded within each
P89LPC9331/9341/9351/9361 device. The NXP ISP facility has made in-system
programming in an embedded application possible with a minimum of additional expense
in components and circuit board area. The ISP function uses five pins (V
RXD, and RST). Only a small connector needs to be available to interface your application
to an external circuit in order to use this feature.
The P89LPC9331/9341/9351/9361 contains two special flash elements: the Boot Vector
and the Boot Status bit. Following reset, the P89LPC9331/9341/9351/9361 examines the
contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution
starts at location 0000H, which is the normal start address of the user’s application code.
When the Boot Status bit is set to a value other than zero, the contents of the Boot Vector
are used as the high byte of the execution address and the low byte is set to 00H.
Table 10
factory-provided bootloader is pre-programmed into the address space indicated and
uses the indicated bootloader entry point to perform ISP functions. This code can be
erased by the user.
Remark: Users who wish to use this loader should take precautions to avoid erasing the
1 kB sector that contains this bootloader. Instead, the page erase function can be used to
erase the first eight 64-byte pages located in this sector.
A custom bootloader can be written with the Boot Vector set to the custom bootloader, if
desired.
Table 10.
Device
P89LPC9331
shows the factory default Boot Vector setting for these devices. A
Default boot vector values and ISP entry points
All information provided in this document is subject to legal disclaimers.
Default
boot vector
0FH
Rev. 5 — 10 January 2011
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
Default
bootloader
entry point
0F00H
Default bootloader
code range
0E00H to 0FFFH
© NXP B.V. 2011. All rights reserved.
1 kB sector
range
0C00H to 0FFFH
DD
, V
SS
, TXD,
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