P89LPC9341FDH,512 NXP Semiconductors, P89LPC9341FDH,512 Datasheet - Page 62

• Manufacturer Part Number: P89LPC9341FDH,512
• Description: IC 80C51 MCU FLASH 8K 28-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC9341FDH,512

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 28-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8 bit, 4 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935288632512

NXP Semiconductors
P89LPC9331_9341_9351_9361
Product data sheet
8.6.1 Fixed channel, single conversion mode
8.6.2 Fixed channel, continuous conversion mode
8.6.3 Auto scan, single conversion mode
8.6.4 Auto scan, continuous conversion mode
8.6.5 Dual channel, continuous conversion mode
8.6 ADC operating modes
A single input channel can be selected for conversion. A single conversion will be
performed and the result placed in the result register pair which corresponds to the
selected input channel. An interrupt, if enabled, will be generated after the conversion
completes.
In P89LPC9351/9361, in fixed channel mode, the PGA channel selection is dependent on
the ADC channel selection. If PGA is enabled, all the selected channels for A/D
conversion will be amplified and the gain amplify level is the same.
A single input channel can be selected for continuous conversion. The results of the
conversions will be sequentially placed in the four result register. The user may select
whether an interrupt can be generated after every four conversions. Additional conversion
results will again cycle through the four result register, overwriting the previous results.
Continuous conversions continue until terminated by the user.
In P89LPC9351/9361, in fixed channel mode, the PGA channel selection is independent
and can be different to A/D conversion channel selection. If different, the gain of the
selected ADC channel is 1.
Any combination of the four input channels can be selected for conversion. A single
conversion of each selected input will be performed and the result placed in the result
register which corresponds to the selected input channel. An interrupt, if enabled, will be
generated after all selected channels have been converted. If only a single channel is
selected this is equivalent to single channel, single conversion mode.
In P89LPC9351/9361, in auto scan mode, the PGA channel selection is dependent on the
ADC channel selection. If PGA is enabled, all the selected channel for A/D conversion will
be amplified and the gain amplify level is the same.
Any combination of the four input channels can be selected for conversion. A conversion
of each selected input will be performed and the result placed in the result register which
corresponds to the selected input channel. An interrupt, if enabled, will be generated after
all selected channels have been converted. The process will repeat starting with the first
selected channel. Additional conversion results will again cycle through the eight result
register pairs, overwriting the previous results. Continuous conversions continue until
terminated by the user.
In P89LPC9351/9361, in auto scan mode, the PGA channel selection is dependent on the
ADC channel selection. If PGA is enabled, all the selected channel for A/D conversion will
be amplified and the gain amplify level is the same.
This is a variation of the auto scan continuous conversion mode where conversion occurs
on two user-selectable inputs. The result of the conversion of the first channel is placed in
the result register, ADxDAT0. The result of the conversion of the second channel is placed
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 January 2011
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
© NXP B.V. 2011. All rights reserved.
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