P89LPC9341FDH,512 NXP Semiconductors, P89LPC9341FDH,512 Datasheet - Page 64

• Manufacturer Part Number: P89LPC9341FDH,512
• Description: IC 80C51 MCU FLASH 8K 28-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC9341FDH,512

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 28-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8 bit, 4 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935288632512

NXP Semiconductors
P89LPC9331_9341_9351_9361
Product data sheet
8.10 Clock divider
8.11 Power-down and Idle mode
8.9 DAC output to a port pin with high output impedance
An early detection mechanism exists when the interrupt criteria has been selected to be
outside the boundary limits. In this case, after the four MSBs have been converted, these
four bits are compared with the four MSBs of the boundary high and low registers. If the
four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits)
an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt
criteria, the boundary limits will again be compared after all 8 bits have been converted.
The boundary status register (BNDSTA0) flags the channels which caused a boundary
interrupt.
Each ADC’s DAC block can be output to a port pin. In this mode, the ADxDAT3 register is
used to hold the value fed to the DAC. After a value has been written to the DAC (written
to ADxDAT3), the DAC output will appear on the channel 3 pin.
The ADC requires that its internal clock source be in the range of 320 kHz to 8 MHz to
maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is
provided for this purpose.
In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit
Idle mode when the conversion is completed if the A/D interrupt is enabled. In
Power-down mode or Total Power-down mode, the A/D, PGA and temperature sensor do
not function. If the PGAs, temperature sensor or the A/D are enabled, they will consume
power. Power can be reduced by disabling the PGA, temperature sensor and A/D.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 January 2011
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
© NXP B.V. 2011. All rights reserved.
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