P89LPC9341FDH,512 NXP Semiconductors, P89LPC9341FDH,512 Datasheet - Page 63

• Manufacturer Part Number: P89LPC9341FDH,512
• Description: IC 80C51 MCU FLASH 8K 28-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC9341FDH,512

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 28-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8 bit, 4 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935288632512

NXP Semiconductors
P89LPC9331_9341_9351_9361
Product data sheet
8.6.6 Single step mode
8.7.1 Timer triggered start
8.7.2 Start immediately
8.7.3 Edge triggered
8.7.4 Dual start immediately
8.7 Conversion start modes
8.8 Boundary limits interrupt
in result register, ADxDAT1. The first channel is again converted and its result stored in
ADxDAT2. The second channel is again converted and its result placed in ADxDAT3. An
interrupt is generated, if enabled, after every set of four conversions (two conversions per
channel).
In P89LPC9351/9361, in dual channel mode, the PGA channel selection is independent
and can be different to A/D conversion channel selection. If different, the gain of the
selected ADC channel is 1.
This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any
combination of the four input channels can be selected for conversion. After each channel
is converted, an interrupt is generated, if enabled, and the A/D waits for the next start
condition. May be used with any of the start modes.
In P89LPC9351/9361, in single step mode, the PGA channel selection is independent and
can be different to A/D conversion channel selection. If different, the gain of the selected
ADC channel is 1.
An A/D conversion is started by the overflow of Timer 0. Once a conversion has started,
additional Timer 0 triggers are ignored until the conversion has completed. The Timer
triggered start mode is available in all ADC operating modes.
Programming this mode immediately starts a conversion. This start mode is available in all
ADC operating modes.
An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has
started, additional edge triggers are ignored until the conversion has completed. The edge
triggered start mode is available in all ADC operating modes.
Programming this mode starts a synchronized conversion of both A/D converters. This
start mode is available in all A/D operating modes. Both A/D converters must be in the
same operating mode. In the continuous conversion modes, both A/D converters must
select an identical number of channels. Any trigger of either A/D will start a simultaneous
conversion of both A/Ds.
Each of the A/D converters has both a high and low boundary limit register. The user may
select whether an interrupt is generated when the conversion result is within (or equal to)
the high and low boundary limits or when the conversion result is outside the boundary
limits. An interrupt will be generated, if enabled, if the result meets the selected interrupt
criteria. The boundary limit may be disabled by clearing the boundary limit interrupt
enable.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 January 2011
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
© NXP B.V. 2011. All rights reserved.
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