R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 115
![MCU 128KKB FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
Price
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Part Number:
R4F24568NVFQV
Manufacturer:
REA
Quantity:
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Part Number:
R4F24568NVFQV
Manufacturer:
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H8S/2456, H8S/2456R, H8S/2454 Group
3.2.2
SYSCR selects saturation operation for the MAC instruction, controls CPU access to the flash
memory control registers, sets the external bus mode, and enables or disables on-chip RAM.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Bit
7, 6
5
4
3
2
Bit Name
⎯
MACS
⎯
FLSHE
⎯
System Control Register (SYSCR)
Initial Value
All 1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
⎯
Descriptions
Reserved
The initial value should not be modified.
MAC Saturation Operation Control
Selects either saturation operation or non-saturation
operation for the MAC instruction.
0: MAC instruction performs non-saturation operation
1: MAC instruction performs saturation operation
Reserved
The initial value should not be modified.
Flash Memory Control Register Enable
Controls CPU access to the flash memory control
registers (FLMCR1, FLMDBPR, and FLMSTR). If this
bit is set to 1, the flash memory control registers can
be read from and written to. If this bit is cleared to 0,
the flash memory control registers are not selected.
At this time, the contents of the flash memory control
registers are retained. 0 should be written to this bit in
LSIs other than the flash memory version.
0: Flash memory control registers are not selected for
1: Flash memory control registers are selected for
Reserved
This bit is always read as 0 and cannot be modified.
addresses H'FFFEB0 to H'FFFEB3
addresses H'FFFEB0 to H'FFFEB3
Section 3 MCU Operating Modes
Page 85 of 1392
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