R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 954

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI, IrDA)
15.7.4
Only the internal clock generated by the on-chip baud rate generator is used as transmit/receive
clock in Smart Card interface. In Smart Card interface mode, the SCI operates on a basic clock
with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit rate (fixed at 16 times in
normal asynchronous mode) as determined by bits BCP2 to BCP0. In reception, the SCI samples
the falling edge of the start bit using the basic clock, and performs internal synchronization. As
shown in figure 15.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, 128th,
46th, 64th, 93rd, or 256th pulse of the basic clock, data can be latched at the middle of the bit. The
reception margin is given by the following formula.
Where M: Reception margin (%)
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
Page 924 of 1392
M = ⏐ (0.5 –
N: Ratio of bit rate to clock (N = 32, 64, 372, 256, 93, 128, 186, or 512)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
M = (0.5 – 1/2 × 372) × 100%
Receive Data Sampling Timing and Reception Margin
= 49.866%
2N
1
) – (L – 0.5) F –
⏐D – 0.5⏐
N
(1 + F) ⏐ × 100 [%]
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010