R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 65

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Type
Address
bus
Data bus
Address/
data
multiplexed
bus
Bus
control
Symbol
A23 to A0
D15 to D0 80 to 73,
AD15 to
AD0
CS7 to
CS0
AS
AH
RD
HWR
LWR
BREQ-A
BREQ-B
PLQP0144KA-A PTLG0145JB-A
31 to 26,
24 to 19,
17 to 11,
9 to 5
71,
69 to 63
80 to 73,
71,
69 to 63
38 to 35,
110 to 107
90
90
89
88
87
132
134
H8S/2456, H8S/2456R
J3, K2, J1, K4,
H3, J2, J4, G3,
H2, G1, H4, G4,
F1, G2, F3, E4,
E1, F2, E3, D1,
D3, D2, C3, C1
K11, K12, L13,
L11, M12, L12,
N13, M13, N11,
M11, N10, L9,
M10, N9, K10, L8
K11, K12, L13,
L11, M12, L12,
N13, M13, N11,
M10, N10, K10,
L10, M9, N9, K9
M2, N2, M1, L1,
A13, A12, B13,
C12
G10
G10
G12
H11
J13
D5
B5
Pin No.
PLQP0120LA-A,
PLQP0120KA-A
29 to 23,
21 to 18,
16 to 9,
7 to 3
68 to 61,
59,
57 to 51
68 to 61,
59,
57 to 51
29, 71, 70, 106,
92 to 89
75
75
74
73
72
108
110
H8S/2454
I/O
Output These pins output an address.
Input/
output
Input/
output
Output Signals that select division areas 7
Output When this pin is low, it indicates that
Output Signal for holding the address when
Output When this pin is low, it indicates that
Output Strobe signal indicating that an
Output Strobe signal indicating that an
Input
Function
These pins constitute a bidirectional
data bus. When an address/data
multiplexed I/O space is accessed,
an address is also output.
These pins output an address, and
input or output data.
to 0 in the external address space
address output on the address bus
is valid.
an address/data multiplexed I/O
space is being accessed.
the external address space is being
read.
external address space is to be
written to, and the upper half (D15
to D8) of the data bus is enabled.
Also functions as the write enable
signal for accessing the DRAM
space.
external address space is to be
written to, and the lower half (D7 to
D0) of the data bus is enabled.
The external bus master requests
the bus to this LSI.
Section 1 Overview
Page 35 of 1392