R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 696

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 I/O Ports
• PF0/WAIT-A/ADTRG0-B/SCS0-C/OE-A (H8S/2454 Group)
• Modes 1, 2, 4, and 7 (EXPE = 1)
Page 666 of 1392
OEE
RMTS2 to
RMTS0
WAITE
WAITS
SSU settings
PF0DDR
Pin function
OEE
RMTS2 to
RMTS0
WAITE
WAITS
SSU settings
PF0DDR
Pin function
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit WAITE in BCR of the bus controller, bit OEE in DRAMCR, bits MSS,
CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of SSU, bits TRGS1, TRGS0, and
EXTRGS in ADCR_0 of ADC, bit OES in PFCR2, bits ADTRG0S and WAITS in PFCR4,
bits SCS0S1 and SCS0S0 in PFCR5, and bit PF0DDR.
PF0 input
input*
(1) in table below
(1) in table below
PF0
0
0
3
output
PF0
output
1
PF0
1
SCS0-C
input*
below
(2) in
table
SCS0-C
⎯
input*
0
0
below
(2) in
table
⎯
0
0
3
Settings other than that for areas 2 to 5 as DRAM
3
SCS0-C
below
(4) in
table
I/O*
0
SCS0-C
below
(4) in
table
I/O*
5
0
5
SCS0-C
output*
below
(3) in
table
⎯
SCS0-C
output*
ADTRG0-B input*
below
(3) in
table
ADTRG0-B input*
4
⎯
WAIT-A
4
input
⎯
⎯
⎯
0
0
1
WAIT-A
input
⎯
⎯
0
PF0 input
2
below
(1) in
table
2
0
PF0 input
below
(1) in
table
H8S/2456, H8S/2456R, H8S/2454 Group
0
prohibited
Setting
⎯
1
1
prohibited
Setting
1
REJ09B0467-0350 Rev. 3.50
⎯
SCS0-C
1
1
input*
below
(2) in
table
0
1
3
SCS0-C
input*
below
(2) in
table
prohibited
(3) (4) in
Setting
0
below
table
0
3
Jul 07, 2010
prohibited
(3) (4) in
Setting
Areas 2 to
below
table
OE-A*
DRAM
space
output
5 are
0
⎯
⎯
⎯
⎯
1