R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 24

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 USB Function Module (USB) .........................................................949
16.1 Features.............................................................................................................................. 949
16.2 Input/Output Pins............................................................................................................... 950
16.3 Register Descriptions ......................................................................................................... 951
16.4 Interrupt Sources................................................................................................................ 986
16.5 Operation ........................................................................................................................... 988
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16.3.1 Interrupt Flag Register 0 (IFR0) ........................................................................... 952
16.3.2 Interrupt Flag Register 1 (IFR1) ........................................................................... 954
16.3.3 Interrupt Flag Register 2 (IFR2) ........................................................................... 955
16.3.4 Interrupt Enable Register 0 (IER0) ....................................................................... 956
16.3.5 Interrupt Enable Register 1 (IER1) ....................................................................... 957
16.3.6 Interrupt Enable Register 2 (IER2) ....................................................................... 958
16.3.7 Interrupt Select Register 0 (ISR0)......................................................................... 959
16.3.8 Interrupt Select Register 1 (ISR1)......................................................................... 960
16.3.9 Interrupt Select Register 2 (ISR2)......................................................................... 961
16.3.10 EP0i Data Register (EPDR0i)............................................................................... 961
16.3.11 EP0o Data Register (EPDR0o) ............................................................................. 962
16.3.12 EP0s Data Register (EPDR0s) .............................................................................. 962
16.3.13 EP1 Data Register (EPDR1) ................................................................................. 963
16.3.14 EP2 Data Register (EPDR2) ................................................................................. 963
16.3.15 EP3 Data Register (EPDR3) ................................................................................. 964
16.3.16 EP0o Receive Data Size Register (EPSZ0o) ........................................................ 964
16.3.17 EP1 Receive Data Size Register (EPSZ1) ............................................................ 964
16.3.18 Data Status Register 0 (DASTS0)......................................................................... 965
16.3.19 Data Status Register 1 (DASTS1)......................................................................... 966
16.3.20 Trigger Register 0 (TRG0) ................................................................................... 967
16.3.21 Trigger Register 1 (TRG1) ................................................................................... 968
16.3.22 FIFO Clear Register 0 (FCLR0) ........................................................................... 969
16.3.23 FIFO Clear Register 1 (FCLR1) ........................................................................... 970
16.3.24 Endpoint Stall Register 0 (EPSTL0)..................................................................... 971
16.3.25 Endpoint Stall Register 1 (EPSTL1)..................................................................... 972
16.3.26 Stall Status Register 1 (STLSR1) ......................................................................... 973
16.3.27 DMA Transfer Setting Register (DMAR) ............................................................ 974
16.3.28 Configuration Value Register (CVR) ................................................................... 977
16.3.29 Control Register (CTLR) ...................................................................................... 977
16.3.30 Endpoint Information Register (EPIR) ................................................................. 979
16.3.31 Transceiver Test Register 0 (TRNTREG0) .......................................................... 983
16.3.32 Transceiver Test Register 1 (TRNTREG1) .......................................................... 984
16.5.1 Initial Settings....................................................................................................... 988