R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 427
![MCU 128KKB FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
R4F24568NVFQV
Manufacturer:
REA
Quantity:
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Company:
Part Number:
R4F24568NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 7 DMA Controller (DMAC)
7.5.13
Relation between DMAC and External Bus Requests, Refresh Cycles,
and EXDMAC*
When the DMAC accesses external space, contention with a refresh cycle, EXDMAC cycle*, or
external bus release cycle may arise. In this case, the bus controller will suspend the transfer and
insert a refresh cycle, EXDMAC cycle*, or external bus release cycle, in accordance with the
external bus priority order, even if the DMAC is executing a burst transfer or block transfer. (An
external access by the DTC or CPU, which has a lower priority than the DMAC, is not executed
until the DMAC releases the external bus.)
When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after
an external write cycle. The external read cycle and external write cycle are inseparable, and so the
bus cannot be released between these two cycles.
When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC
cycle may be executed at the same time as a refresh cycle, EXDMAC cycle*, or external bus
release cycle.
Note: * Not supported by the H8S/2454 Group.
REJ09B0467-0350 Rev. 3.50
Page 397 of 1392
Jul 07, 2010
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