R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 327

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML
differ according to the settings of the IDLC bit. The timing in this case is illustrated in figures 6.85
and 6.86. In write access, DQMU and DQML are not in accordance with the settings of the IDLC
bit. The timing in this case is illustrated in figure 6.87.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Precharge-sel
DQMU, DQML
Address bus
HWR, LWR
Data bus
CKE
CAS
RAS
WE
RD
φ
Figure 6.85 Example of Idle Cycle Operation in RAS Down Mode
PALL ACTV READ
address
Column
(Read in Different Area) (IDLC = 0, CAS Latency 2)
T
Continuous synchronous
DRAM space read
p
address
address
Row
Row
T
r
T
Column address 1
c1
T
cl
High
High
T
c2
External space read
T
External address
External address
1
NOP
T
2
T
3
Idle cycle
T
Continuous synchronous
DRAM space read
i
Section 6 Bus Controller (BSC)
Column address 2
READ
T
c1
T
Cl
NOP
Page 297 of 1392
T
c2