R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 21

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.5 Usage Notes ....................................................................................................................... 820
Section 13 8-Bit Timers (TMR).........................................................................821
13.1 Features.............................................................................................................................. 821
13.2 Input/Output Pins............................................................................................................... 823
13.3 Register Descriptions ......................................................................................................... 824
13.4 Operation ........................................................................................................................... 833
13.5 Operation Timing............................................................................................................... 835
13.6 Operation with Cascaded Connection................................................................................ 839
13.7 Interrupt Sources................................................................................................................ 840
13.8 Usage Notes ....................................................................................................................... 841
12.4.7 Inverted Pulse Output ........................................................................................... 818
12.4.8 Pulse Output Triggered by Input Capture ............................................................. 819
12.5.1 Module Stop Function Setting .............................................................................. 820
12.5.2 Operation of Pulse Output Pins............................................................................. 820
13.3.1 Timer Counter (TCNT)......................................................................................... 825
13.3.2 Time Constant Register A (TCORA).................................................................... 825
13.3.3 Time Constant Register B (TCORB) .................................................................... 825
13.3.4 Timer Control Register (TCR).............................................................................. 826
13.3.5 Timer Counter Control Register (TCCR) ............................................................. 827
13.3.6 Timer Control/Status Register (TCSR)................................................................. 829
13.4.1 Pulse Output.......................................................................................................... 833
13.4.2 Reset Input ............................................................................................................ 834
13.5.1 TCNT Incrementation Timing .............................................................................. 835
13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs .................. 836
13.5.3 Timing of Timer Output when Compare-Match Occurs....................................... 836
13.5.4 Timing of Compare Match Clear.......................................................................... 837
13.5.5 Timing of TCNT External Reset........................................................................... 837
13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 838
13.6.1 16-Bit Counter Mode ............................................................................................ 839
13.6.2 Compare Match Count Mode................................................................................ 839
13.7.1 Interrupt Sources and DTC Activation ................................................................. 840
13.7.2 A/D Converter Activation..................................................................................... 840
13.8.1 Contention between TCNT Write and Clear......................................................... 841
13.8.2 Contention between TCNT Write and Increment ................................................. 842
13.8.3 Contention between TCOR Write and Compare Match ....................................... 843
13.8.4 Contention between Compare Matches A and B .................................................. 844
13.8.5 Switching of Internal Clocks and TCNT Operation ............................................. 844
13.8.6 Mode Setting with Cascaded Connection ............................................................. 846
13.8.7 Module Stop Function Setting .............................................................................. 846
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