R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 15

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 EXDMA Controller (EXDMAC) ......................................................407
8.1
8.2
8.3
8.4
8.5
8.6
Section 9 Data Transfer Controller (DTC) ........................................................477
9.1
9.2
9.3
9.4
Features.............................................................................................................................. 407
Input/Output Pins............................................................................................................... 409
Register Descriptions ......................................................................................................... 410
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
Operation ........................................................................................................................... 423
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.4.10 EXDMAC Bus Cycles (Single Address Mode) .................................................... 452
8.4.11 Examples of Operation Timing in Each Mode ..................................................... 457
8.4.12 Ending EXDMA Transfer..................................................................................... 471
8.4.13 Relationship between EXDMAC and Other Bus Masters .................................... 472
Interrupt Sources................................................................................................................ 473
Usage Notes ....................................................................................................................... 475
Features.............................................................................................................................. 477
Register Descriptions ......................................................................................................... 479
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
Activation Sources............................................................................................................. 485
Location of Register Information and DTC Vector Table ................................................. 487
EXDMA Source Address Register (EDSAR)....................................................... 411
EXDMA Destination Address Register (EDDAR)............................................... 411
EXDMA Transfer Count Register (EDTCR)........................................................ 412
EXDMA Mode Control Register (EDMDR) ........................................................ 414
EXDMA Address Control Register (EDACR) ..................................................... 419
Transfer Modes..................................................................................................... 423
Address Modes ..................................................................................................... 424
EXDMA Transfer Requests.................................................................................. 428
Bus Modes ............................................................................................................ 429
Transfer Modes..................................................................................................... 431
Repeat Area Function ........................................................................................... 434
Registers during EXDMA Transfer Operation ..................................................... 437
Channel Priority Order.......................................................................................... 441
EXDMAC Bus Cycles (Dual Address Mode) ...................................................... 445
DTC Mode Register A (MRA) ............................................................................. 479
DTC Mode Register B (MRB).............................................................................. 481
DTC Source Address Register (SAR)................................................................... 482
DTC Destination Address Register (DAR)........................................................... 482
DTC Transfer Count Register A (CRA) ............................................................... 482
DTC Transfer Count Register B (CRB)................................................................ 482
DTC Enable Registers A to I (DTCERA to DTCERI) ......................................... 483
DTC Vector Register (DTVECR)......................................................................... 483
DTC Control Register (DTCCR) .......................................................................... 484
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