R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 485
![MCU 128KKB FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24568NVFQV
Manufacturer:
REA
Quantity:
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Company:
Part Number:
R4F24568NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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H8S/2456, H8S/2456R, H8S/2454 Group
(3)
Figure 8.26 shows an example of single address mode transfer activated by the EDREQ pin falling
edge.
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the EXDMA single cycle, acceptance resumes
after the end of the single cycle, and EDREQ pin low level sampling is performed again; this
sequence of operations is repeated until the end of the transfer.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle start; EDREQ pin high level sampling is started at rise of φ.
[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of single cycle.
EDREQ Pin Falling Edge Activation Timing
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
φ
EDREQ
Address bus
EDACK
EXDMA control
Channel
Figure 8.26 Example of Single Address Mode Transfer Activated
Idle
[1]
Minimum 3 cycles
Request
Bus release
by EDREQ Pin Falling Edge
[2]
clearance period
Single
[3]
Request
Transfer source/
EXDMA
destination
single
cycle
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
[5]
clearance period
Single
[6]
Section 8 EXDMA Controller (EXDMAC)
Request
Transfer source/
EXDMA
destination
single
cycle
Idle
Acceptance
resumed
[7]
Bus release
Page 455 of 1392
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