R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 20

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.5 Interrupt Sources................................................................................................................ 772
11.6 DTC Activation.................................................................................................................. 776
11.7 DMAC Activation.............................................................................................................. 776
11.8 A/D Converter Activation.................................................................................................. 776
11.9 Operation Timing............................................................................................................... 777
11.10 Usage Notes ....................................................................................................................... 786
Section 12 Programmable Pulse Generator (PPG) ............................................ 797
12.1 Features.............................................................................................................................. 797
12.2 Input/Output Pins............................................................................................................... 799
12.3 Register Descriptions ......................................................................................................... 800
12.4 Operation ........................................................................................................................... 809
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11.9.1 Input/Output Timing ............................................................................................. 777
11.9.2 Interrupt Signal Timing ........................................................................................ 782
11.10.1 Module Stop Function Setting .............................................................................. 786
11.10.2 Input Clock Restrictions ....................................................................................... 786
11.10.3 Caution on Cycle Setting ...................................................................................... 787
11.10.4 Contention between TCNT Write and Clear Operations ...................................... 787
11.10.5 Contention between TCNT Write and Increment Operations............................... 788
11.10.6 Contention between TGR Write and Compare Match .......................................... 789
11.10.7 Contention between Buffer Register Write and Compare Match ......................... 790
11.10.8 Contention between TGR Read and Input Capture............................................... 791
11.10.9 Contention between TGR Write and Input Capture.............................................. 792
11.10.10 Contention between Buffer Register Write and Input Capture........................... 793
11.10.11 Contention between Overflow/Underflow and Counter Clearing ...................... 794
11.10.12 Contention between TCNT Write and Overflow/Underflow ............................. 795
11.10.13 Multiplexing of I/O Pins..................................................................................... 795
11.10.14 Interrupts and Module Stop State ....................................................................... 795
12.3.1 Next Data Enable Registers H and L (NDERH, NDERL).................................... 801
12.3.2 Output Data Registers H and L (PODRH, PODRL)............................................. 802
12.3.3 Next Data Registers H and L (NDRH, NDRL)..................................................... 803
12.3.4 PPG Output Control Register (PCR) .................................................................... 806
12.3.5 PPG Output Mode Register (PMR) ...................................................................... 807
12.4.1 Output Timing ...................................................................................................... 810
12.4.2 Sample Setup Procedure for Normal Pulse Output............................................... 811
12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)........... 812
12.4.4 Non-Overlapping Pulse Output............................................................................. 813
12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output............................... 815
12.4.6 Example of Non-Overlapping Pulse Output
(Example of Four-Phase Complementary Non-Overlapping Output) .................. 816