R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 335

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
Table 6.12 shows whether there is an idle cycle insertion or not in the case of mixed accesses to
normal space and DRAM space/continuous synchronous DRAM space.
Table 6.12 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Previous Access
Normal space read
DRAM/continuous
synchronous
DRAM *
space read
Synchronous DRAM Space
Next Access
Normal space read
(different area)
DRAM/continuous
synchronous DRAM *
space read
Normal space write
DRAM/continuous
synchronous DRAM *
space write
Normal space read
DRAM/continuous
synchronous DRAM *
space read
Normal space write
DRAM/continuous
synchronous DRAM*
space write
ICIS2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ICIS1
0
1
0
1
⎯
⎯
⎯
⎯
0
1
0
1
⎯
⎯
⎯
⎯
ICIS0
⎯
⎯
⎯
⎯
0
1
0
1
⎯
⎯
⎯
⎯
0
1
0
1
DRMI
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
1
⎯
0
1
⎯
0
1
⎯
0
1
Section 6 Bus Controller (BSC)
IDLC
⎯
0
1
⎯
0
1
⎯
0
1
⎯
0
1
⎯
⎯
0
1
⎯
⎯
0
1
⎯
⎯
0
1
⎯
⎯
0
1
Idle cycle
Disabled
1 state inserted
2 states inserted
Disabled
1 state inserted
2 states inserted
Disabled
1 state inserted
2 states inserted
Disabled
1 state inserted
2 states inserted
Disabled
Disabled
1 state inserted
2 states inserted
Disabled
Disabled
1 state inserted
2 states inserted
Disabled
Disabled
1 state inserted
2 states inserted
Disabled
Disabled
1 state inserted
2 states inserted
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