R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 66

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 Overview
Page 36 of 1392
Type
Bus
control
Symbol
BREQO-A
BREQO-B
BACK-A
BACK-B
UCAS
LCAS
DQMU *
DQML *
RAS2
RAS3
RAS4 *
RAS5 *
RAS *
CAS *
WE *
1
1
1
2
2
1
1
PLQP0144KA-A PTLG0145JB-A
130
133
131
135
85
86
85
86
109
110
35
36
109
110
35
H8S/2456, H8S/2456R
B6
A6
C7
C6
H12
H10
H12
H10
A12
A13
L1
M1
A12
A13
L1
Pin No.
PLQP0120LA-A,
PLQP0120KA-A
106
109
107
111
70
71
⎯
⎯
91
92
⎯
⎯
⎯
⎯
⎯
H8S/2454
I/O
Output External bus request signal when
Output Indicates the bus is released to the
Output Upper column address strobe signal
Output Lower column address strobe signal
Output Upper data mask enable signal for
Output Lower-data mask enable signal for
Output Row address strobe signal for the
Output Row address strobe signal for the
Output Column address strobe signal for
Output Write enable signal for the
H8S/2456, H8S/2456R, H8S/2454 Group
Function
the internal bus master accesses an
external space in the external bus
release state.
external bus master.
for accessing the 16-bit DRAM
space. Also functions as the column
address strobe signal for accessing
the 8-bit DRAM space.
for accessing the 16-bit DRAM
space.
accessing the 16-bit continuous
synchronous DRAM space. Also
functions as the data mask enable
signal for accessing the 8-bit
continuous synchronous DRAM
space.
accessing the 16-bit continuous
synchronous DRAM interface
space.
DRAM when the DRAM interface is
set. Row address strobe signal
when areas 2 to 5 are set as the
continuous DRAM space.
synchronous DRAM when the
synchronous DRAM interface is set.
the synchronous DRAM when the
synchronous DRAM interface is set.
synchronous DRAM when the
synchronous DRAM interface is set.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010