R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 282
![MCU 128KKB FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
R4F24568NVFQV
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 6 Bus Controller (BSC)
6.7.13
DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface
When burst mode is selected on the DRAM interface, the DACK and EDACK output timing can
be selected with the DDS and EDDS bits in DRAMCR. When DRAM space is accessed in DMAC
or EXDMAC single address mode at the same time, these bits select whether or not burst access is
to be performed.
(1)
When DDS = 1 or EDDS = 1
Burst access is performed by determining the address only, irrespective of the bus master. With
the DRAM interface, the DACK or EDACK output goes low from the T
state.
c1
Figure 6.53 shows the DACK or EDACK output timing for the DRAM interface when DDS = 1 or
EDDS = 1.
Page 252 of 1392
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
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