R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 380
![MCU 128KKB FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 7 DMA Controller (DMAC)
MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When
modifying these registers, the channel to be modified should be halted.
7.3.7
DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can
be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The
TEND pin is available only for channel B in short address mode. Except for the block transfer
mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents
reaches 0 regardless of the activation source. In the block transfer mode, a transfer end signal
asserts in the transfer cycle in which the block counter contents reaches 0.
Page 350 of 1392
Bit
7, 6
5
4
3 to 0
Bit Name
⎯
TEE1
TEE0
⎯
DMA Terminal Control Register (DMATCR)
Initial Value
All 0
0
0
All 0
R/W
⎯
R/W
R/W
⎯
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Transfer End Enable 1
Enables or disables transfer end pin 1 (TEND1)
output.
0: TEND1 pin output disabled
1: TEND1 pin output enabled
Transfer End Enable 0
Enables or disables transfer end pin 0 (TEND0)
output.
0: TEND0 pin output disabled
1: TEND0 pin output enabled
Reserved
These bits are always read as 0 and cannot be
modified.
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
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