R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 504

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 EXDMA Controller (EXDMAC)
The transfer end interrupt can be cleared either by clearing the IRF bit to 0 in EDMDR within the
interrupt handling routine, or by re-setting the transfer counter and address registers and then
setting the EDA bit to 1 in EDMDR to perform transfer continuation processing. An example of
the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 8.46.
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Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which Transfer
[1] Write set values to the registers (transfer counter, address registers, etc.).
[2] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. When 1 is written to the EDA
[3] The interrupt handling routine is ended with an RTE instruction, etc.
[4] Clear the IRF bit to 0 in EDMDR by first reading 1 from it, then writing 0.
[5] After the interrupt handling routine is ended with an RTE instruction, etc., interrupt masking is
[6] Write set values to the registers (transfer counter, address registers, etc.).
[7] Write 1 to the EDA bit in EDMDR to restart EXDMA operation.
bit, the IRF bit in EDMDR is automatically cleared to 0 and the interrupt source is cleared.
cleared.
(RTE instruction execution)
exception handling routine
End of interrupt handling
Change register settings
Transfer end interrupt
End of transfer restart
Transfer continuation
Write 1 to EDA bit
processing
processing
routine
End Interrupt Occurred
[1]
[2]
[3]
of interrupt handling routine
Transfer restart after end
End of interrupt handling
Change register settings
End of transfer restart
Write 1 to EDA bit
Clear IRF bit to 0
processing
routine
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
[4]
[5]
[6]
[7]
Jul 07, 2010