R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 374
R4F24568NVFQV
Manufacturer Part Number
R4F24568NVFQV
Description
MCU 128KKB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24568NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 7 DMA Controller (DMAC)
Page 344 of 1392
Bit
6
Bit Name
DTE1
0
Initial Value
R/W
R/W
Description
Data Transfer Enable 1
Enables or disables DMA transfer for the
activation source selected by the DTF3 to DTF0
bits in DMACR of channel 1.
When DTE1 = 0, data transfer is disabled and the
activation source is ignored. If the activation
source is an internal interrupt, an interrupt request
is issued to the CPU or DTC. If the DTE1 bit is
cleared to 0 when DTIE1 = 1, the DMAC regards
this as indicating the end of a transfer, and issues
a transfer end interrupt request to the CPU.
When DTE1 = 1 and DTME1 = 1, data transfer is
enabled and the DMAC waits for a request by the
activation source. When a request is issued by the
activation source, DMA transfer is executed.
[Clearing conditions]
•
•
•
[Setting condition]
When 1 is written to the DTE1 bit after reading
DTE1 = 0
When initialization is performed
When the specified number of transfers have
been completed
When 0 is written to the DTE1 bit to forcibly
suspend the transfer, or for a similar reason
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
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