R4F24568NVFQV Renesas Electronics America, R4F24568NVFQV Datasheet - Page 27

• Manufacturer Part Number: R4F24568NVFQV
• Description: MCU 128KKB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 D/A Converter................................................................................1091
19.1 Features............................................................................................................................ 1091
19.2 Input/Output Pins............................................................................................................. 1093
19.3 Register Descriptions ....................................................................................................... 1093
19.4 Operation ......................................................................................................................... 1096
19.5 Usage Notes ..................................................................................................................... 1098
Section 20 Synchronous Serial Communication Unit (SSU) ..........................1099
20.1 Features............................................................................................................................ 1099
20.2 Input/Output Pins............................................................................................................. 1101
20.3 Register Descriptions ....................................................................................................... 1102
20.4 Operation ......................................................................................................................... 1115
20.5 Interrupt Requests ............................................................................................................ 1138
20.6 Usage Note....................................................................................................................... 1139
Section 21 RAM ..............................................................................................1141
19.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3)........................................... 1093
19.3.2 D/A Control Register 23 (DACR23) .................................................................. 1094
19.5.1 Module Stop Function Setting ............................................................................ 1098
19.5.2 D/A Output Hold Function in Software Standby Mode...................................... 1098
20.3.1 SS Control Register H (SSCRH) ........................................................................ 1103
20.3.2 SS Control Register L (SSCRL) ......................................................................... 1105
20.3.3 SS Mode Register (SSMR) ................................................................................. 1106
20.3.4 SS Enable Register (SSER) ................................................................................ 1107
20.3.5 SS Status Register (SSSR).................................................................................. 1108
20.3.6 SS Control Register 2 (SSCR2) .......................................................................... 1111
20.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................. 1113
20.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................. 1114
20.3.9 SS Shift Register (SSTRSR)............................................................................... 1114
20.4.1 Transfer Clock .................................................................................................... 1115
20.4.2 Relationship of Clock Phase, Polarity, and Data ................................................ 1115
20.4.3 Relationship between Data Input/Output Pins and Shift Register ...................... 1116
20.4.4 Communication Modes and Pin Functions ......................................................... 1117
20.4.5 SSU Mode........................................................................................................... 1119
20.4.6 SCS Pin Control and Conflict Error.................................................................... 1130
20.4.7 Clock Synchronous Communication Mode ........................................................ 1131
20.6.1 Module Stop Function Setting ............................................................................ 1139
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