HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 129

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.3.3
• When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction
• When a PC break interrupt is generated at a DTC transfer address
6.3.4
The operation when a PC break interrupt is set for an instruction fetch at the address after a
SLEEP instruction is shown below.
• When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
• When the SLEEP instruction causes a transition to software standby mode:
PC break exception handling is executed after all data transfers have been completed and the
EEPMOV.B instruction has ended.
PC break exception handling is executed after the DTC has completed the specified number of
data transfers, or after data for which the DISEL bit is set to 1 has been transferred.
sleep mode:
After execution of the SLEEP instruction, a transition is not made to sleep mode, and PC break
interrupt handling is executed. After execution of PC break interrupt handling, the instruction
at the address after the SLEEP instruction is executed (figure 6.2 (A)).
After execution of the SLEEP instruction, a transition is made to the respective mode, and PC
break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2
(B)).
Operation in Transitions to Power-Down Modes
Notes on PC Break Interrupt Handling
Figure 6.2 Operation in Power-Down Mode Transitions
Execution of instruction
instruction execution
after sleep instruction
PC break exception
handling
SLEEP
(A)
instruction execution
respective mode
Transition to
Rev. 7.00 Sep. 11, 2009 Page 93 of 566
SLEEP
Section 6 PC Break Controller (PBC)
(B)
REJ09B0211-0700