HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 25

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 PC Break Controller (PBC)
Figure 6.1
Figure 6.2
Section 7 Bus Controller
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
Section 8 Data Transfer Controller (DTC)
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Figure 8.7
Figure 8.8
Figure 8.9
Figure 8.10
Figure 8.11
Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Figure 10.7
Figure 10.8
Figure 10.9
Figure 10.10 Example of Synchronous Operation Setting Procedure ......................................... 203
Figure 10.11 Example of Synchronous Operation....................................................................... 204
Figure 10.12 Compare Match Buffer Operation.......................................................................... 205
Figure 10.13 Input Capture Buffer Operation ............................................................................. 206
Figure 10.14 Example of Buffer Operation Setting Procedure.................................................... 206
Figure 10.15 Example of Buffer Operation (1) ........................................................................... 207
Figure 10.16 Example of Buffer Operation (2) ........................................................................... 208
Block Diagram of PC Break Controller ................................................................... 90
Operation in Power-Down Mode Transitions .......................................................... 93
On-Chip Memory Access Cycle............................................................................... 97
On-Chip Support Module Access Cycle .................................................................. 98
On-Chip HCAN Module Access Cycle (Wait States Inserted) ................................ 99
On-Chip MMT Module Access Cycle ................................................................... 100
Block Diagram of DTC .......................................................................................... 104
Block Diagram of DTC Activation Source Control ............................................... 110
Correspondence between DTC Vector Address and Register Information ............ 111
Flowchart of DTC Operation ................................................................................. 114
Memory Mapping in Normal Mode ....................................................................... 115
Memory Mapping in Repeat Mode ........................................................................ 116
Memory Mapping in Block Transfer Mode ........................................................... 118
Chain Transfer Operation....................................................................................... 119
DTC Operation Timing (Example in Normal Mode or Repeat Mode) .................. 120
DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2).................................... 121
DTC Operation Timing (Example of Chain Transfer) ........................................... 121
Block Diagram of TPU .......................................................................................... 162
Example of Counter Operation Setting Procedure ................................................. 197
Free-Running Counter Operation ........................................................................... 198
Periodic Counter Operation.................................................................................... 199
Example of Setting Procedure for Waveform Output by Compare Match............. 199
Example of 0 Output/1 Output Operation .............................................................. 200
Example of Toggle Output Operation .................................................................... 200
Example of Input Capture Operation Setting Procedure ........................................ 201
Example of Input Capture Operation ..................................................................... 202
Rev. 7.00 Sep. 11, 2009 Page xxiii of xxxiv
REJ09B0211-0700