HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 16

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.3 Register Descriptions ......................................................................................................... 164
10.4 Operation............................................................................................................................ 197
10.5 Interrupts ............................................................................................................................ 223
10.6 DTC Activation.................................................................................................................. 225
10.7 A/D Converter Activation .................................................................................................. 225
10.8 Operation Timing............................................................................................................... 226
10.9 Usage Notes ....................................................................................................................... 234
Section 11 Motor Management Timer (MMT) .................................................245
11.1 Features .............................................................................................................................. 245
Rev. 7.00 Sep. 11, 2009 Page xiv of xxxiv
REJ09B0211-0700
10.3.1 Timer Control Register (TCR) .............................................................................. 166
10.3.2 Timer Mode Register (TMDR) ............................................................................. 171
10.3.3 Timer I/O Control Register (TIOR) ...................................................................... 173
10.3.4 Timer Interrupt Enable Register (TIER) ............................................................... 190
10.3.5 Timer Status Register (TSR)................................................................................. 192
10.3.6 Timer Counter (TCNT)......................................................................................... 195
10.3.7 Timer General Register (TGR) ............................................................................. 195
10.3.8 Timer Start Register (TSTR)................................................................................. 195
10.3.9 Timer Synchro Register (TSYR) .......................................................................... 196
10.4.1 Basic Functions..................................................................................................... 197
10.4.2 Synchronous Operation......................................................................................... 203
10.4.3 Buffer Operation ................................................................................................... 205
10.4.4 Cascaded Operation .............................................................................................. 209
10.4.5 PWM Modes ......................................................................................................... 211
10.4.6 Phase Counting Mode ........................................................................................... 216
10.8.1 Input/Output Timing ............................................................................................. 226
10.8.2 Interrupt Signal Timing......................................................................................... 230
10.9.1 Module Stop Mode Setting ................................................................................... 234
10.9.2 Input Clock Restrictions ....................................................................................... 234
10.9.3 Caution on Period Setting ..................................................................................... 234
10.9.4 Contention between TCNT Write and Clear Operations...................................... 235
10.9.5 Contention between TCNT Write and Increment Operations............................... 236
10.9.6 Contention between TGR Write and Compare Match .......................................... 237
10.9.7 Contention between Buffer Register Write and Compare Match ......................... 238
10.9.8 Contention between TGR Read and Input Capture............................................... 239
10.9.9 Contention between TGR Write and Input Capture.............................................. 240
10.9.10 Contention between Buffer Register Write and Input Capture ............................. 241
10.9.11 Contention between Overflow/Underflow and Counter Clearing......................... 242
10.9.12 Contention between TCNT Write and Overflow/Underflow................................ 243
10.9.13 Multiplexing of I/O Pins ....................................................................................... 243
10.9.14 Interrupts in Module Stop Mode........................................................................... 243