HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 130

IC H8S MCU FLASH 128K 80QFP

HD64F2612FA20

Manufacturer Part Number
HD64F2612FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2612FA20

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
43
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Part Number:
HD64F2612FA20
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RENESAS/瑞萨
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HD64F2612FA20J
Manufacturer:
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Section 6 PC Break Controller (PBC)
6.3.5
While the break interrupt enable bit is set to 1, instruction execution is one state later than usual.
• For 1-word branch instructions (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, and RTS) in on-chip
• When break interruption by instruction fetch is set, the set address indicates on-chip ROM or
• When break interruption by instruction fetch is set and a break interrupt is generated, if the
• When break interruption by instruction fetch is set and a break interrupt is generated, if the
Rev. 7.00 Sep. 11, 2009 Page 94 of 566
REJ09B0211-0700
ROM or RAM.
RAM space, and that address is used for data access, the instruction that executes the data
access is one state later than in normal operation.
executing instruction immediately preceding the set instruction has one of the addressing
modes shown below, and that address indicates on-chip ROM or RAM, the instruction will be
one state later than in normal operation.
Addressing modes: @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24,
@aa:32, @(d:8,PC), @(d:16,PC), @@aa:8
executing instruction immediately preceding the set instruction is NOP or SLEEP, or has
#xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the
instruction will be one state later than in normal operation.
When Instruction Execution is Delayed by One State

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