HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 13

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.7
Section 6 PC Break Controller (PBC) .................................................................89
6.1
6.2
6.3
6.4
Section 7 Bus Controller......................................................................................97
7.1
5.6.2
5.6.3
5.6.4
5.6.5
Usage Notes ......................................................................................................................... 86
5.7.1
5.7.2
5.7.3
5.7.4
Features ................................................................................................................................ 89
Register Descriptions ........................................................................................................... 90
6.2.1
6.2.2
6.2.3
6.2.4
Operation.............................................................................................................................. 92
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Usage Notes ......................................................................................................................... 95
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
Basic Timing ........................................................................................................................ 97
7.1.1
7.1.2
7.1.3
7.1.4
Interrupt Control Mode 2 ........................................................................................ 81
Interrupt Exception Handling Sequence ................................................................. 83
Interrupt Response Times ....................................................................................... 85
DTC Activation by Interrupt................................................................................... 86
Contention between Interrupt Generation and Disabling........................................ 86
Instructions that Disable Interrupts ......................................................................... 87
When Interrupts are Disabled ................................................................................. 87
Interrupts during Execution of EEPMOV Instruction............................................. 88
Break Address Register A (BARA) ........................................................................ 90
Break Address Register B (BARB)......................................................................... 91
Break Control Register A (BCRA) ......................................................................... 91
Break Control Register B (BCRB).......................................................................... 92
PC Break Interrupt Due to Instruction Fetch .......................................................... 92
PC Break Interrupt Due to Data Access.................................................................. 92
Notes on PC Break Interrupt Handling ................................................................... 93
Operation in Transitions to Power-Down Modes ................................................... 93
When Instruction Execution is Delayed by One State ............................................ 94
Module Stop Mode Setting ..................................................................................... 95
PC Break Interrupts................................................................................................. 95
CMFA and CMFB .................................................................................................. 95
PC Break Interrupt when DTC is Bus Master......................................................... 95
PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP,
TRAPA, RTE, or RTS Instruction .......................................................................... 95
I Bit Set by LDC, ANDC, ORC, or XORC Instruction .......................................... 95
PC Break Set for Instruction Fetch at Address Following Bcc Instruction............. 96
PC Break Set for Instruction Fetch at Branch Destination Address of Bcc
Instruction ............................................................................................................... 96
On-Chip Memory Access Timing (ROM, RAM) ................................................... 97
On-Chip Support Module Access Timing............................................................... 98
On-Chip HCAN Module Access Timing ................................................................ 99
On-Chip MMT Module Access Timing................................................................ 100
Rev. 7.00 Sep. 11, 2009 Page xi of xxxiv
REJ09B0211-0700