HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 158

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 Data Transfer Controller (DTC)
Table 8.5
Mode
Normal
Repeat
Block transfer
Legend:
N: Block size (initial setting of CRAH and CRAL)
Table 8.6
Bus width
Access states
Execution
status
Note:
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
For example, when the DTC vector address table is located in the on-chip ROM, normal mode is
set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for
the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Rev. 7.00 Sep. 11, 2009 Page 122 of 566
REJ09B0211-0700
Object to be Accessed
* Cannot be used in this LSI.
Number of execution states = I · S
Vector read
Register information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation
DTC Execution Status
Number of States Required for Each Execution Status
Vector Read
I
1
1
1
S
S
S
S
S
S
S
Register Information
Read/Write
J
6
6
6
I
J
K
K
L
L
M
RAM
Chip
On-
32
—
1
1
1
1
1
1
I
+ Σ (J · S
ROM
Chip
On-
16
—
1
1
1
1
1
1
J
On-Chip I/O
+ K · S
Registers
—
—
8
2
2
4
2
4
Data Read
K
1
1
N
K
16
—
—
+ L · S
2
2
2
2
2
1
L
—
) + M · S
2
4
2
4
2
4
Data Write
L
1
1
N
External Devices *
8
6 + 2m
6 + 2m
6 + 2m
3 + m
3 + m
—
3
M
Internal
Operations
M
3
3
3
—
2
2
2
2
2
2
16
3 + m
3 + m
3 + m
3 + m
3 + m
—
3