HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 529

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MSTPCRC
Bit
7
6
5
4
3
2
1
0
Note:
20.2
When the SCK0 to SCK2 bits in SCKCR are set to 1, the operating mode changes to medium-
speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on
the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK0 to SCK2 bits. Bus masters
(DTC) other than the CPU also operate in medium-speed mode. On-chip supporting modules other
than bus masters always operate on the high-speed clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
Medium-speed mode is cleared by clearing all of bits SCK0 to SCK2 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is
made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored.
When the SLEEP instruction is executed with the SSBY bit = 1, operation shifts to the software
standby mode. When software standby mode is cleared by an external interrupt, medium-speed
mode is restored.
Bit Name
MSTPC7 *
MSTPC6 *
MSTPC5 *
MSTPC4
MSTPC3
MSTPC2
MSTPC1 *
MSTPC0 *
* MSTPA7 is a readable/writable bit with an initial value of 0 and should always be written
Medium-Speed Mode
with 0.
MSTPA4, MSTPA2, MSTPA0, MSTPB4 to MSTPB0, MSTPC7 to MSTPC5, MSTPC1,
and MSTPC0 are readable/writable bits with an initial value of 1 and should always be
written with 1.
Initial Value
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Module
PC break controller (PBC)
Controller Area Network (HCAN)
Motor Management Timer (MMT)
Rev. 7.00 Sep. 11, 2009 Page 493 of 566
Section 20 Power-Down Modes
REJ09B0211-0700